clock synchronization

[Altera_Forum]

I'm currently using a PPL to generate 120MHz ADC clock, and this clock should be aligned with a pulse (denoted as "pulse") falling edge when the synchronization signal (denoted as "SYNC") is high. Both "pulse" and "SYNC" are input signals from another peripheral. The "pulse" has the period of 1s.  

 I'm considering to use "SYNC" as the reset signal for the PLL, but it does not work well. Can anyone give me some hints? Thanks.

[Altera_Forum]

You may want to clarify your specification for aligned in terms of phase deviation. Can we assume, that the sync pulse is phase locked to your primary clock source? Also, can you accept a alignment duration of multiple sync periods? 

 Depending on some specification details, the design isn't necessarily feasible, I think.

[Altera_Forum]

The problem rest on that the ADC clock should be aligned with the "pulse"; that is, their falling edge should show up at the same time for each period of the "pulse" when the "SYNC" is active. I'm considering to let the rising edge of the "SYNC" reset the PLL and then the falling edge of the "pulse" should enable the PLL. However, I don't know how to implement it? :(

[Altera_Forum]

The issue of enabling the PLL at pulse falling edge is not going to work because the PLL needs time to lock. I wonder if you can do it at all with a simple PLL. You will need to think of how to lock the pulse with your 120 clk in some sort of feedback loop(altera PLL may have feedback inputs, never used them)

[Altera_Forum]

It surely doesn't work with a simple PLL. Without additional information, I'm also unable to determine, if it can work at all.