Hello,
I'm starting with vhdl, and i'm try to write any kind of comaprator with memory of the out signal.
Can anyboidy help me..
Program have to check state of input from keypad (ps2) and check it is signal of a letter. if pressed keypad is a letter then on the out will be signal of these key
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bufor IS
PORT(in: IN STD_LOGIC_VECTOR (21 downto 0);
out: OUT STD_LOGIC_VECTOR (7 downto 0));
END ENTITY;
ARCHITECTURE mem OF bufor IS
shared variable li1 : std_logic_vector(7 downto 0);
shared variable li2 : std_logic_vector(7 downto 0);
BEGIN
process (in) is
begin
li1 := "00000000";
li2 := "00000000";
li1 := in(8 downto 1);
-- checking of keypad key
if (((li2) /= (li1))and (li1=( X"21" OR X"23" OR X"24" OR X"2B" OR X"34" OR X"33" OR X"43" OR X"3B" OR X"42" OR X"4B" OR X"3A" OR X"31" OR X"44" OR X"4D" OR X"15" OR X"2D" OR X"1B" OR X"2C" OR X"3C" OR X"2A" OR X"1D" OR X"22" OR X"35" OR X"1A"))) then
li2 := li1;
end if;
out <= li2;
end process;
end mem;
