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i am using the FPP configuration scheme with MAXII & a flash device
i need to switch now to FPP with compression. do i need to change the MSEL pin settings? or can i just program the FLASH with compressed file? i really dont want to wire the MSEL now after the board is ready...Link Copied
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As far as I know, most of FPGA does require the MSEL change. However, some of devices does not...
For example Cyclon* does not require MSEL change. Stratix* will require MSEL change. Check the configuration document on the Altera website.- Mark as New
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What device are you working with. I know the Cyclone III LS devices due not support compression in FPP mode.
Pete- Mark as New
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im using Stratix IV. ive changed the MSEL but couldnt configure the FPGA.
i have tried creating the compressed file in Q10.1 but still, no success.- Mark as New
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Let me double check that you have regular uncompressed FPP working or not.
If working, will it work with the Q10.1 compiled and generated FPGA data? After Q9.1 the pof file format has changed(format which will be written in to Flash). If you stick same version as the PFL in MAX2, then it should be fine. It means, the PFL block in MAX2 and FPGA sof generated Quartus version needs to be same version. If you use Q10.0 for MAX2, Q10.0 for FPGA, then PFL won't have issue. If the PFL is not working even for the uncompressed, then you just need to get it work first. Compressed data will requires x4 of the clock cycle to un-compress. Compressed data will be about half of its original FPGA data, so it's roughly takes x2 of configuration time compare to un-compressed data configuration. If you have watchdog timer, you might need to consider about this as well.
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