conflicting VCCIO settings

[ahmad_zaklouta]

I am getting this error in Quartus for Agilex-I series FPGA:

Error(11924): Bank '3B' has conflicting VCCIO settings
    Error(11928): 'fmc_a_clk1_m2c_p~pad' with I/O standard True Differential Signaling, was constrained to be within bank '3B'
        Info(11929): '1.5V' is a valid VCCIO value
    Error(11928): 'fmc_a_la_n(0)~pad' with I/O standard 1.2 V, was constrained to be within bank '3B'
        Info(11929): '1.2V' is a valid VCCIO value

but both of them have the same IO-standard "True Deferential Signaling", I don't understand where it is getting I/O standard 1.2 V from.

[Farabi]

Hello,

Is it possible to share the skeleton design, so I can see the pin assignment in pin planner?

regards,

Farabi

[Farabi]

Hello,

Referring to this link : https://www.intel.com/content/www/us/en/docs/programmable/683301/current/differential-i-o-standards-specifications.html

The 1.2V if you set the IO as RX only. In LVDS option, need to select the implementation of RX/TX so it can use 1.5V standard.

regards,

Farabi

[Farabi]

Hello,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

regards,

Farabi