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Hi all,
I'm designing a biometric system in RTL using verilog. But I keep getting this warning during compilation.warning: 2 hierarchies have connectivity warnings - see the connectivity checks report folder.
I wonder how to resolve this warning and where is that "connectivity checks report folder" located? Thank in advance, Regards, ty6
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--- Quote Start --- Hi all, I'm designing a biometric system in RTL using verilog. But I keep getting this warning during compilation.
warning: 2 hierarchies have connectivity warnings - see the connectivity checks report folder.
I wonder how to resolve this warning and where is that "connectivity checks report folder" located? Thank in advance, Regards, ty6 --- Quote End --- Hi, you find the folder "Connectivity Checks" in the Compilation report under "Analysis & Synthesis" Kind regards GPK
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Hi all,
The automatic display of the Compilation Report itself can be disabled in the settings of Quartus. To activate the report you can use CTRL+R, then you can proceede as mentioned by GPK in the reply above. To activate the compilation report manually: go to "Processing" [Top Menu]/ "Compilation Report" Kind Regards, Johi.
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