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constraining a data bus with two fpga's

Altera_Forum
Honored Contributor II
‎06-21-2010 03:15 PM
1,395 Views

Hi all, 

I have currently a data bus which connects two FPGA's. Therefore, input and output delays are dependent on each other. Could someone explain me this dependency or give me an example in TimeQuest ? 

 

Best Regards, 

Joel
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