content addressable memory

[Altera_Forum]

is there any way to have content addressable memory(CAM) in CYCLONE IV E families????

[Altera_Forum]

CAM are hiddeously slow.

[Altera_Forum]

i didn't get it. is it possible or not?

[Altera_Forum]

Sure, depending on your requirements you could either implement it with embedded ram, or logic. Logic implementations can be a little expensive in terms of resources, but they're more flexible. Do you need cam, or tcam? Check out Altera's advanced synthesis cookbook, there are some examples in there you can look over.

[Altera_Forum]

I need four or five CAM blocks in 32-bit * 256 size and cyclone IV E is available. (thanks anyway for your help :) )

[Altera_Forum]

The worst case for your CAM is a 256 clock cycle latency.

[Altera_Forum]

If you implemented it in logic, that would be a little resource intensive. How big is the cyclone, how fast does the cam need to run, and how much other stuff are you going to need to shove into the part?

[Altera_Forum]

it is my BS project and i am kind of free to choose the details. i read the cookbook you referred. but it doesn't contain much about CAMs. is there anywhere else to help me? 

that pdf gives no information about the details. should i use a megafunction? how can i turn logic elements into CAM????? (thanks again.)

[Altera_Forum]

You just use a memory with a counter for the address and some SM to control the reading of data. when you find the data, you stop the count.