cpu0_deflags4 interrupt

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

cpu0_deflags4 interrupt

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Hi,

I'm working on software running on a Cyclone V SoC HPS, and I occasionally get an interrupt being

triggered on GIC vector 45. According to table 9-3: gic interrupt map this equals cpu0_deflags4.

Apart from this reference I cant seem to find any info on this specific interrupt source, i.e. how/why

it is triggered and how to handle it, so any information on these 'deflags' irqs is welcome.

Regards,

Wieant

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