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Hi,all,I'm using the ArriaV GX FPGA Development Kit Board to test the custom phy.(software version:QII12.0,chip:5AGXFB3H4F40C5ES).I have successfully completed data transmission at duplex mode.And my application is:Source(TX) -> Sink(RX).So I Create a TX only and an RX only custom IP.But When I use the SignalTap to capture the receive data,the trigger clock is 'rx_clkout'.But the SignalTap status is "Waiting for clock".The pins of TX only/RX only are as same as the Duplex mode. I also simulate the project by modelsim,and find the rx_clkout is always high.
My configuration of the custom phy(RX only): general:Parameter validation rules: Custom Mode of operation: RX Number of lanes: 1 Enable lane bonding: off FPGA fabric ransceiver interface widh: 16 PCS-PMA interface Width: 10 Ddata rate: 3125 Mbps Input clock frequency: 125.0MHz Create rx_coreclkin port: off Create rx_recoverd_clk port: off Create optional ports: off Avalon data interfaces: off Enabled embedded reset controller: on pcs options:
Word alignment mode: Manual Create optional word aligner status ports: off Word aligner pattern length: 10 Word alignment pattern: 0101111100 Enable run length violation checking: off Enable rate match FIFO: on Rate match insertion/deletion +ve disparity pattern:10100010010101111100 Rate match insertion/deletion -ve disparity pattern: 10101011011010000011 Create optional Rate Match FIFO status ports:off Enable 8B/10B encoder/decoder: on Enable manual disparity control: off Create optional 8B10B status ports: off thank you!
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Hi,I try to trun off the "Enable rate match FIFO",and the 'rx_clkout' signal present,Why can't trun on it? .My application like that,C2C(chip-to-chip) transmission between two chips,the source is TX only and sink is RX only.The chips have different local clock which in the different board.Without the Rate match FIFO,how can I ensure that the FIFO doesnot underflow or overflow due to per million(ppm) difference between the clocks?Waiting for your reply,thanks again.

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