cyc3 LVDS_RX for camera link

[Altera_Forum]

I want to instantiate an ALTLVDS_RX megafunction and an external PLL in my design for the purpose of deserializing camera link video. 

 The camera I am using runs at 65MHz for a pixel clock.  I have attached a pic of the standard camera link settings.  When I try to configure the ALTLVDS_RX megafunction for this purpose using the megawizard, I see this text in the info bar:  Warning: Selecting to not register the outputs of the receiver Warning: will require that they be registered in the logic fed by the receiver. Info: Using the external PLL mode requires that Info: - The fast clock (running at data rate / 2) from the PLL feeds tx_inclock Info: - The slow clock (fast clock / DESERIALIZATION_FACTOR) from the PLL feeds tx_syncclock Info: - The inputs be pre-registered in the logic feeding the transmitter by a clock (running at data rate / DESERIALIZATION_FACTOR) Info: Using the external PLL mode requires that Info: - The fast clock (running at data rate / 2) from the PLL feeds rx_inclock Info: - The slow clock (fast clock / DESERIALIZATION_FACTOR) from the PLL feeds rx_syncclock Info: - The read clock (2 * fast clock / DESERIALIZATION_FACTOR) from the PLL feeds rx_readclock Info: - The outputs be registered in the logic fed by the receiver by the read clock. Info: The receiver starts capturing the LVDS stream at the fast clock edge.  Can anyone tell me what each of the three clock rates should be for fast clock, slow clock, and read clock? It sounds like they should be:  fast clock = data rate / 2,  data rate = 7 * 65MHz  fast clock = 227.5MHz??  slow clock = 65MHz??  read clock = 2 * fast clock / DESERIALIZATION_FACTOR = 65MHz read clock = 2 * 227.5 MHz / 7 = 65MHz??  Why the need for two 65MHz clocks here? Are they phase shifted from each other? By what amount?  See the camera link serialization pattern attached.  Thanks!           

[Altera_Forum]

I can't answer the question in detail, but if you want to know which PLL settings are expected by the LVDS_RX block, you can implement a variant with internal PLL and see, how the PLL is set up.  

 An odd deserialization factor is involving a rather complex structure, because fast clock uisn't an integer multiply of slow clock.

[Altera_Forum]

I always do what FvM suggested. I've asked that the LVDS block just get created with an external PLL by default, and then the user can edit it from there if they want to. Hopefully that gets done someday, because the setup is not intuitive. 

Remember that if you generate one with an internal PLL, create an .sdc that has "derive_pll_clocks" in it. This should add multicycles from the fabric to the LVDS block that you can just copy into your design.

[Altera_Forum]

--- Quote Start ---   Can anyone tell me what each of the three clock rates should be for fast clock, slow clock, and read clock? It sounds like they should be:  fast clock = data rate / 2,  data rate = 7 * 65MHz  fast clock = 227.5MHz??  slow clock = 65MHz??  read clock = 2 * fast clock / DESERIALIZATION_FACTOR = 65MHz read clock = 2 * 227.5 MHz / 7 = 65MHz?? Why the need for two 65MHz clocks here? Are they phase shifted from each other? By what amount?      --- Quote End ---   De-serialisation is done using DDR circuitry -> so the fast clock is 65 * 7 / 2 = 227.5 MHz. Because we can not directly do something with an odd factor, the ALT-LVDS block deserialises two subsequent transmissions and it needs a clock to synchronise the resulting 14 shifted bits using base clock divided by 2 -> 32.5 MHz. If you use the sync/multiplexer output options (not using M9K RAM blocks) the 14 bits are then fed into a multiplexer which uses this same 1/2 clock to select the first or second 7-bit output word. Finally you the use the third 1-to-1 pll clock output (-> 65 MHz) to drive the logic receiving the output of the multiplexer.  A good idea is to just compile the MegaWizard generated ALT_LVDS function on its own and then look in Tools->Netlist Viewers-> RTL Viewer what it produces.  If, for comparison, you generate the block with an internal PLL, as FvM suggests, you can see that the phase shift needed for the all three clocks is minus 1/2 of the bit-time (look in side any of the 3 generated .v files), and that the PLL has been set up in source-synchronous mode. Once again, in RTL Viewer you can appreciate how the generated clocks are used.   --- Quote Start ---  Remember that if you generate one with an internal PLL, create an .sdc that has "derive_pll_clocks" in it. This should add multicycles from the fabric to the LVDS block that you can just copy into your design.  --- Quote End ---   How does the "derive_pll_clocks" add the multicycles? What if we use an external PLL?