cyclone 3 restricted fmax

[Altera_Forum]

Hi, 

 at some point during my work I needed to use a higher frequency clock in Cyclone 3 (EP3C16) speedgrade -8 and thought of a 400 MHz clock. In the Cyclone 3 Handbook volume 2 table 1-19 it is specified 402 MHz for this core. However after running implementation TimeQuest reports an fmax of ~250 MHz with the mention that it is restricted to 238 MHz due to minimum period restriction (tmin). Where did this tmin come from? I haven't seen it in the datasheet. Any hints?

[Altera_Forum]

The fmax will come from your design. 

 The datasheet fmax of 402MHz is the theoretical fmax. The actual fmax will depend on your design.

[Altera_Forum]

Tricky, 

 you haven't read my post carefully... I know about fmax and design but i have no idea why the 238 restricted fmax (second column in timequest->report fmax) is there... my understanding it should be 402 instead of 238... right?

[Altera_Forum]

I think, I have seen similar things. My explanation for it was that some global clock networks have a lower fmax then others, but this is just a guess. Have you constrained your clock, so that the fitter knows that you want to achieve 400MHz? 

 Thomas  P.S.: I suppose you have not specified a duty-cycle for your clock different to 50%?

[Altera_Forum]

P.P.S.: Or do you have a M9K-block connected to this clock? That has a fmax of 238MHz with -8 speedgrade.

[Altera_Forum]

--- Quote Start ---  P.P.S.: Or do you have a M9K-block connected to this clock? That has a fmax of 238MHz with -8 speedgrade.  --- Quote End ---    Yes, Quartus knows about the frequency, i constrained the PLL input and the 400 is inclk x 10. Duty cycle is 50%.  There is a small altera fifo generated here (built around an M9K), i guess you're right. I should generate it in logic (size only 4x16). Hope it works!

[Altera_Forum]

yes, it was the M9K. thanks!