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Hi,
For extraxting data from a 576Mbps serial datastream (subLVDS) with a DDR clock of 288MHz I would like to use the transceiver inputs of the Cyclone V. Can I do this easily? Can I use the transceiver input as a diff. IO? Thanks.Link Copied
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--- Quote Start --- For extraxting data from a 576Mbps serial datastream (subLVDS) with a DDR clock of 288MHz I would like to use the transceiver inputs of the Cyclone V. Can I do this easily? Can I use the transceiver input as a diff. IO? --- Quote End --- You can, but it will take a little extra work. Although the transceivers accept LVDS signals, they do not operate like an LVDS SERDES. The transceiver receivers contain clock-and-data recovery (CDR) units with a PLL that normally initially locks to a reference clock, and then transitions to locking to data transitions (so that the transceiver clock captures the data in the center of the eye-pattern). Since your LVDS signal has both data and clock, its likely that the data stream does not have enough transitions to guarantee the operation of the CDR. You would need to configure the transceiver CDR in lock-to-reference mode, and then use the DDR clock as the reference to the CDR PLL. Since the CDR would remain in lock-to-reference mode, the data capture is unlikely to be ideal (the received high-speed clock would not be in the center of the data eye). You can deal with this in a couple of ways; program the PLL phase-shift (via the scan-chain), or over-sample the LVDS signal, and add logic to look for the "correct" samples. Since your data stream is at the low-end of the supported data rates, you'll likely need to oversample anyway. Cheers, Dave
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Hi Dave,
thank you very much for your answer! It seems to be that it will be extra work indeed but because I'm not familiar with these transceivers, it will take a lot of extra work. The exactual design is that I must extract data from 24 subLVDS channels of serial data of 576Mbps devided in 4 groups. Each group has his own DDR clock of 288MHz. I'll have to think about it. Thank you! Marc --- Quote Start --- You can, but it will take a little extra work. Although the transceivers accept LVDS signals, they do not operate like an LVDS SERDES. The transceiver receivers contain clock-and-data recovery (CDR) units with a PLL that normally initially locks to a reference clock, and then transitions to locking to data transitions (so that the transceiver clock captures the data in the center of the eye-pattern). Since your LVDS signal has both data and clock, its likely that the data stream does not have enough transitions to guarantee the operation of the CDR. You would need to configure the transceiver CDR in lock-to-reference mode, and then use the DDR clock as the reference to the CDR PLL. Since the CDR would remain in lock-to-reference mode, the data capture is unlikely to be ideal (the received high-speed clock would not be in the center of the data eye). You can deal with this in a couple of ways; program the PLL phase-shift (via the scan-chain), or over-sample the LVDS signal, and add logic to look for the "correct" samples. Since your data stream is at the low-end of the supported data rates, you'll likely need to oversample anyway. Cheers, Dave --- Quote End ---- Mark as New
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Hi,
The Cyclone V transceiver's minimum supported data rate is 614Mbps which is higher than your 576Mbps requirement. You might want to consider oversampling to meet the data rate specification of the transceiver.- Mark as New
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I am trying to use subLVDS I/O on the SOC cyclone dev kit. I have a camera with DDR2 outputs, do I need to wire the data and clocks to the transceiver ports on the FPGA, or can I just use a macrocell configuration on any differential pins (that support sub-LVDS)? I am not getting sensible data from the camera as yet when I use bank 8A for the subLVDS data and clk inputs.
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--- Quote Start --- I am trying to use subLVDS I/O on the SOC cyclone dev kit. I have a camera with DDR2 outputs, do I need to wire the data and clocks to the transceiver ports on the FPGA, or can I just use a macrocell configuration on any differential pins (that support sub-LVDS)? I am not getting sensible data from the camera as yet when I use bank 8A for the subLVDS data and clk inputs. --- Quote End --- Hi, I use DIFFIO_RX sub_LVDS input of bank 4A for the serial data input and CLK3P/N of the clock input of that bank also sub_LVDS (DDR). That works nicely. You have to take care of impedance matching and a good cable or other connection. To convert the serial data stream to parallel data, ALTLVDS_RX function is used. Hope this helps.
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OK, that is encouraging. I'm using the HSMC interconnect at present. Engineering our own PCB should improve things. Experienced a lot of grief with using Quartus 13.1. had to upgrade to 15.1 to fix the ALTLVDS__RX to fix issues with the internal PLL.
Thanks again. Regards Phil- Mark as New
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Hi,
you make me curious about the camera/image sensor you are using. Can you tell me what type of HSMC connector you use and what kind of dev. board? Best regards. --- Quote Start --- OK, that is encouraging. I'm using the HSMC interconnect at present. Engineering our own PCB should improve things. Experienced a lot of grief with using Quartus 13.1. had to upgrade to 15.1 to fix the ALTLVDS__RX to fix issues with the internal PLL. Thanks again. Regards Phil --- Quote End ---- Mark as New
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--- Quote Start --- Hi, I use DIFFIO_RX sub_LVDS input of bank 4A for the serial data input and CLK3P/N of the clock input of that bank also sub_LVDS (DDR). That works nicely. You have to take care of impedance matching and a good cable or other connection. To convert the serial data stream to parallel data, ALTLVDS_RX function is used. Hope this helps. --- Quote End --- interesting applications,
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good sharing
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