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AWu6
Beginner
228 Views

cyclone v FPGA上,针对多个GE网口,该如何做时序约束?

单个GE网口的RGMII接口时钟约束和内部逻辑时钟约束我知道如何做,也调试验证过,时序收敛的情况下,数据收发没有问题,多个网口的约束,只是单独约束各自的时钟的情况下,会报很多交叉的时钟的negtive slack,而且数据收发基本上是混乱的。这个需要如何解决?

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2 Replies
109 Views

Hi,

 

Could you provide the design for investigation? What is the software version?

 

Thanks.

Best regards,

KhaiY

109 Views

Hi,

 

Do you have any updates?

 

Thanks.

Best regards,

KhaiY

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