Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19335 Discussions

cyclone v FPGA上,针对多个GE网口,该如何做时序约束?

AWu6
Beginner
246 Views

单个GE网口的RGMII接口时钟约束和内部逻辑时钟约束我知道如何做,也调试验证过,时序收敛的情况下,数据收发没有问题,多个网口的约束,只是单独约束各自的时钟的情况下,会报很多交叉的时钟的negtive slack,而且数据收发基本上是混乱的。这个需要如何解决?

0 Kudos
2 Replies
KhaiChein_Y_Intel
127 Views

Hi,

 

Could you provide the design for investigation? What is the software version?

 

Thanks.

Best regards,

KhaiY

KhaiChein_Y_Intel
127 Views

Hi,

 

Do you have any updates?

 

Thanks.

Best regards,

KhaiY

Reply