cyclone v lvds serdes fractional corner pll clocking

[Altera_Forum]

alright people; let's say you use 4 fractional corner plls in cyclone v. all of them drive lvds serdes RX-es and TX-es. but let's say i want to use single dedicated clock input pin for all of the pll clock inputs. obviously that would not work. because there is a separate dedicated clock pin for each of the plls. i don't want to cascade plls, and don't want to use separate dedicated clock pins. so, is there any way to input a clock in a single dedicated pin and distribute that by global clock to all the corner fractional plls while they drive these lvds serdes modules ..? 

 (i already tried, fitter can't do that)

[Altera_Forum]

--- Quote Start ---   is there any way to input a clock in a single dedicated pin and distribute that by global clock to all the corner fractional plls   --- Quote End ---   The fact that Quartus will not let you probably means no.  I had a similar question regarding providing Stratix IV+V transceivers on two sides of an FPGA a common reference clock, and the only acceptable solution to the fitter was to use separate REFCLK pins; one on each side of the FPGA. This indicates it is necessary to use an external clock buffer.  This is not exactly what you want to hear if your board is already built, but if you are performing an analysis of what is possible before you design your board, then I think you will need to have at least two reference clocks, i.e., one to each side of the FPGA, and from there you might be able to lock the fractional PLLs.  Cheers, Dave

[Altera_Forum]

thanks for the answer. rarely people these days have a will to give knowledge to others. 

 no pcb is not yet designed. yeah.. i also noticed that there are specific REFCLK pins on cyclone v and each pin has access to 2 corner plls simultaneously; one for top 2 corner plls and another for bottom 2 corner plls and buffer you mentioned is a good way around. otherwise the clocks will reach REFCLK pins with different propagation delays and will have a phase shift in relation to each other. OR, if i place a crystal oscillator exactly on the middle line of cyclone v; at right or left side ; and use exactly same length traces in this case they will reach REFCLK -s with similar propagation delays and should have no phase shift between each other... well... or i should place a clock buffer and distribute clock to REFCLK-s from there.   another way i guess is to drive clock to these 2 REFCLK - s right from the crystal oscillator, with different trace lengths; then analyze phase difference of the arrival of clocks to the REFCLK-s. and use pll phase shift ability to align pll output clocks to each other and with the incoming clock phase. only limitation here is the fact that phase shift control will not let you to have any value of phase shift. it has fixed increments as i remember. 1.5 degrees or something like this. i am talking too much i know :) but it is so easy to get lost in these things. when i'll get that i was trying to prove a foolishness it will be too late.  my boss tells me that he was spoiled by cyclone iv which allowed single REFCLK pin to reach all the plls on entire fpga. even while these plls were driving serdes lvds. but of course cyclone iv had it's drawbacks. some rx tx pins were not allowed to be placed next to each other and stuff like this. cyclone v overcame that limitation by fixing rx es and tx es in appropriate places. but gave us new limitations with REFCLK use.   one more small question, i tried to use tx pin as an rx. as i remember emulated lvds had an ability to use tx pin as a receiver. but here in cyclone v i can't find a way to switch pins to emulated lvds. they are kinda all fixed true lvds -es with OCT -s in it. cyclone iv had set of banks with emulated lvds pins. cyclone v has only true lvds es...

[Altera_Forum]

--- Quote Start ---  thanks for the answer. rarely people these days have a will to give knowledge to others.   --- Quote End ---   This list is pretty good in that respect :)    --- Quote Start ---   no pcb is not yet designed. yeah..    --- Quote End ---   Excellent. I'm glad to hear that you have enough "experience" to realize that you should synthesize a few designs prior to PCB layout.    --- Quote Start ---   i also noticed that there are specific REFCLK pins on cyclone v and each pin has access to 2 corner plls simultaneously; one for top 2 corner plls and another for bottom 2 corner plls and buffer you mentioned is a good way around. otherwise the clocks will reach REFCLK pins with different propagation delays and will have a phase shift in relation to each other. OR, if i place a crystal oscillator exactly on the middle line of cyclone v; at right or left side ; and use exactly same length traces in this case they will reach REFCLK -s with similar propagation delays and should have no phase shift between each other... well... or i should place a clock buffer and distribute clock to REFCLK-s from there.    --- Quote End ---   SiLabs and Texas Instruments have programmable clock buffers, i.e., devices that can have one or more input references signals, and can generate one or more output signals. Take a look at some of the Terasic/Altera reference boards to see what they use, and then look on the SiLabs or TI web sites. There are several parts that can be programmed via I2C. The main thing to consider is the jitter generated by these devices. Some are capable of generating the reference clock for 10Gbps signals, so for your LVDS application there should be several parts that work fine. Use one or more of the external clock buffer devices and route pins from each buffer to both sides of the device. With two devices, you then have the option of different REFCLK frequencies, but still can have coherent clocks on both sides of the FPGA.    --- Quote Start ---   another way i guess is to drive clock to these 2 REFCLK - s right from the crystal oscillator, with different trace lengths; then analyze phase difference of the arrival of clocks to the REFCLK-s. and use pll phase shift ability to align pll output clocks to each other and with the incoming clock phase. only limitation here is the fact that phase shift control will not let you to have any value of phase shift. it has fixed increments as i remember. 1.5 degrees or something like this. i am talking too much i know :) but it is so easy to get lost in these things. when i'll get that i was trying to prove a foolishness it will be too late.   --- Quote End ---   The PLLs can shift phase in 1/8th of the VCO steps. With say a 1GHz VCO, that is 1ns/8 = 125ps. I'd argue that your PCB design should such that you get it routed first, and then decide whether or not you want to match traces. Given the fact that the clocks need to route to both sides of the FPGA, there's a pretty good chance you'll have closely matched traces without trying too hard.    --- Quote Start ---   one more small question, i tried to use tx pin as an rx. as i remember emulated lvds had an ability to use tx pin as a receiver. but here in cyclone v i can't find a way to switch pins to emulated lvds. they are kinda all fixed true lvds -es with OCT -s in it. cyclone iv had set of banks with emulated lvds pins. cyclone v has only true lvds es...  --- Quote End ---   I don't have an answer for this one. I would do exactly as you are doing and see if Quartus supports it. If it doesn't, then I'd have a look at the handbook and pin configuration guidelines and see if they have comments on the support for emulated LVDS. There's probably an app note that discusses it too.  Cheers, Dave

[Altera_Forum]

Thank you David. i will share my experience after we will solve these problems. so that everyone can use this knowledge in future. my response will not be soon though, because a motherboard will have almost a size of an A4 paper and lots of high speed components on it.

[Altera_Forum]

--- Quote Start ---  i will share my experience after we will solve these problems. so that everyone can use this knowledge in future.   --- Quote End ---   That is an excellent attitude.    --- Quote Start ---   my response will not be soon though, because a motherboard will have almost a size of an A4 paper and lots of high speed components on it.  --- Quote End ---   In that case, here's some more advice. If your high-speed is in the Gbps range, then you may have to consider using Megtron or Nelco 4000-SI materials. If that is the case, then because you are using the PCB manufacturer "controlled impedance" process, it turns out you can get laser drilled microvias from the top-to-first inner layer (or bottom to first inner-layer) essentially for free. Having this option makes it significantly easier to route differential traces for transceivers or LVDS, since you can drop a microvia in the two BGA pads (or right next to the pad) for the differential signal, and then route nice clean differential traces. Depending on where the LVDS signals are located, this can save you a layer in your stackup. Talk to your PCB manufacturer and see what they can provide and what the cost-differential between your options is.  Cheers, Dave