hiwhile implementing the pll using mega function , it generated code with ENTITY pll IS PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ); END pll; but i gave the input inclk0 as 100 MHz, why it is giving IN STD_LOGIC := '0'; please tell me how to generate clock using pll mega function. is it possible to simulate that?
--- Quote Start --- i gave the input inclk0 as 100 MHz, why it is giving IN STD_LOGIC := '0'; --- Quote End --- There's no contradiction. Yes, you have to connect inclk0 to a 100 MHz input clock. But Quartus prefers to assign a default signal level, which take effect, if you don't connect a component's port pin. It doesn't make sense in this case, cause the MegaFunction can't operate in a meaningful way without connecting inclk0. But it's useful in many other cases, e.g. for an optional reset input. It's a general VHDL element, you may want to consult a text book for a detailed syntax description. And yes, PLL operation can be simulated, e.g. by Quartus simulator.
dear fvmthanks for your reply...one doubt i have ask u is i simulated that clock circuit(implemented by mega function). but the generated output clock is coming only after some time, before that e no clock is coming, it showing as before simulation... file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot.jpg file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot-1.jpg file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot-2.jpg file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot-3.jpg file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot-4.jpg
The simulator is reproducing rather exactly the real behaviour of a PLL in this regard, consult the Cyclone III and alt_pll MegaFunction handbook for details on PLL lock behaviour. There are also features as a locked monitor output or automatic PLL reset in case of lock loss.
dear fvm please clarify some doubts regarding cyclone3 pll,1. i used altpll megafunction to generate1733 Hz with 8.192 MHz as input. it accepted but while i simulating it is not giving o/p with that frequency. 2. for all simulations it is giving 700ns delay for output 3.how to cascade plls to get low o/p frequencies 4. in pll what are the functions of signals pfdena,locked 5. how the multiplication and division factors of pll mega functions are related to the M,N, COUNTER VALUE. 6.how to get other o/ps(except dedicated o/p) of pll to externally i/o pins. with regards krishnam raju
Hello eveybody!I'm simulating a pll but an error always appears: Modifying C:\Applications\Modelsim6.1c\win32/../modelsim.ini# Error: Acces denied.# Unable to replace existing ini file (C:\Applications\Modelsim6.1c\win32/../modelsim.ini). File can not be renamed.# ** Error: (vcom-19) Failed to access library 'cycloneiii' at "cycloneiii". Thank you very much for any help! information : I am not in administrator session and I cannot modify anything I didn't create.
Thank you for all!I found the solution: I created a new library called "cycloneiii" exactly the name of the library he didn't access and edited its mapping to the one it should be. By quitting and running again Gate Level simulation, I had my simulation. Now I have another question :) When running the Gate Level simulation, I found that two clocks doesn't have the same phase : there is a difference of some tens of picoseconds. Is this difference from the pll or from modelsim? Thanks