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Hi to all.
I am using quartus prime 16.1.2 to generate the ibis model I / O to do the signal integrity. I have a 3v LVTTL output line (fFPGA) that I have to be connected to an external chip. In "pin planner" if I disable a series termination is generated a ibis model with 27.9 ohms output driver impedance If i put series 25 ohm without calibration is generated a ibis model with with 11.7 ohms output driver impedance. If i put series 50 ohm without calibration is generated a ibis model with with 11.7 ohms output driver impedance also. where am I wrong? I insert the simulations that confirm what I said: BEst regards.Link Copied
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