Hi I am trying to build a memory controller to interface two MT47H32M16BN DDR2 devices to a Cyclone4 GX30 FGG484 FPGA.
I have got the project to compile successfully but when I run the fitter I get error messages:
Error: Cannot place pin mem_dq[14] to location W6
Error: Can't place VREF pin V9 (VREFGROUP_B3_N2) for pin mem_dq[14] of type bi-directional with 1.8-V HSTL
Class I I/O standard at location W6
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin V9
(VREFGROUP_B3_N2) is used on device EP4CGX30CF23C8 -- no more than 9 output/bidirectional pins within
12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially
10 pins driving out
Also on the pin planner i can see 6 of my pins with errors which say "No more than 20 outputs are allowed in a VRefgroup
when Vref is being read from".
Do these messages mean that I cannot interface these two memory devices to this FPGA or should I try moving some of the
IOs onto different pins?
