Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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dangling port&logic

Altera_Forum
Honored Contributor II
‎02-08-2010 05:13 AM
1,956 Views

hello . 

i wrote a program, then i compile it. and it is compiled properly. 

this program has 4 entity. after compliation, i could see entity-4 in RTL viewer but there isn't in technology map viewer completely. further more it hasn't any output. when i checked the "connectivity checks" it reveals that the following info: 

Connected to dangling logic. Logic that only feeds a dangling port will be removed. 

thank you.
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Altera_Forum
Honored Contributor II
‎02-08-2010 06:52 AM
978 Views

hello. 

I could find the problem. i inadvertently commented one of control outputs then the next entity that works with it was dangled.
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