ddr2 high performance ip core

[Altera_Forum]

i am designing PCI2DDR2 interface 

i want to use the ip core with CycIII device. does the core support ECC thats less then 64 bit? the PCI data is 32 bit i am going to interface 10 DDR2 components of 2 Gbit. 5 components of X16 bus to get 72 bit data bus (with ECC), and two sets of that to get 2 Gbyte total size. can i share DQ's between the 2 sets? otherwise i dont have enough pins at CycIII (even the 780 package)..

[Altera_Forum]

The simple thing is, you can share the memory bus for two blocks of memory with separate chip selects. Assigning the 9 or 10 DQS groups to Cyclone III resources is more complicated . There are different combinations allowing different operating speeds, AN445 is specially describing Cyclone III DDR interface. Finally, I don't know details regarding ECC option.

[Altera_Forum]

are you sure i can share DQs? 

should i need to change somthing in the ODT for that?

[Altera_Forum]

Most memory modules have already two ranks or blocks of memory internally, they have basically separate chip selects and ODT signals, also at least two pairs of clock signals. The memory controller is controlling ODT in an appropriate way. However, different techniques have been suggested by memory manufacturers regarding optimal ODT control. The weak point with Altera memory controller and Cyclone II/III or Arria/Stratix II is, that no dynamic on-chip-termination at the FPGA side is present. This feature is starting with Stratix III.