delay for a Sinusoid

Altera_Forum · ‎01-15-2009

I am using an FPGA kit for controlling my power electronic converter. To implement the PLL, I have to give a delay of .005s to a signal whose frequency may range from 20 to 70 Hz. The input is given from a 12 bit ADC. My sampling frequency is 20kHz and I am using a Cyclone device.

How do I implement the logic?

Altera_Forum · ‎01-15-2009

You don't state whether the input is a digital signal, but let's assume it is

(i.e., a square-wave at FPGA-compatible levels)

- Instantiate a 100-bit shift-register clocked at 20KHz. Your signal is the input, and the output is the same, delayed by 50uSec*100= .005s

Wade Hassler

Altera_Forum · ‎01-15-2009

For either digitized analog or digital signal, you can use altshift_taps MegaFunction, as in the below example.


-- CONSTANT CNT_5MS : INTEGER := 500;
  in_beta_delay : altshift_taps
  GENERIC MAP (
    lpm_type => "altshift_taps",
    number_of_taps => 1,
    tap_distance => CNT_5MS,
    width => 16
  )
  PORT MAP (
    clken => phase_pwm_s,
    clock => clk40,
    shiftin => u_Nalpha,
    shiftout => U_Nbeta
  );

Altera_Forum · ‎01-16-2009

The input is given from a 12 bit ADC.Can you please suggest me a solution for this?

Altera_Forum · ‎01-16-2009

My example is for 16 bit data. Just set width to 12.

Altera_Forum · ‎01-22-2009

Hello FvM,

Thank you very much for your reply.In the code you had mentioned earlier, you had given tap distance in terms of time.But in MegaWizard Plug-in manager, how can I give that?

My .v file corresponding to altshift_taps MegaFunction is given below.

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module altshift_taps3 (

clock,

shiftin,

shiftout,

taps);

input clock;

input [11:0] shiftin;

output [11:0] shiftout;

output [143:0] taps;

wire [143:0] sub_wire0;

wire [11:0] sub_wire1;

wire [143:0] taps = sub_wire0[143:0];

wire [11:0] shiftout = sub_wire1[11:0];

altshift_taps altshift_taps_component (

.clock (clock),

.shiftin (shiftin),

.taps (sub_wire0),

.shiftout (sub_wire1),

.aclr (1'b0),

.clken (1'b1));

defparam

altshift_taps_component.lpm_hint = "RAM_BLOCK_TYPE=M512",

altshift_taps_component.lpm_type = "altshift_taps",

altshift_taps_component.number_of_taps = 12,

altshift_taps_component.tap_distance = 100,

altshift_taps_component.width = 12;

Can I change this code to get tap distance mentioned in terms of time?

Altera_Forum · ‎01-22-2009

According to your original post, you won't require taps with your FIFO. In my example cnt_5ms is simply an integer constant, defined above in the code. But you can calculate it from clock frequency and time delay in the code, e.g.

CONSTANT CLK_PWM_kHz : INTEGER = 40;
CONSTANT DELAY_ms5 : INTEGER = 5;
CONSTANT CNT_5MS : INTEGER = CLK_PWM_kHz*DELAY_ms5;

You may want to read the respective Verilog syntax from a manual or text book.