Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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detect a signal was at 1

Altera_Forum
Honored Contributor II
‎08-14-2015 01:14 PM
1,386 Views

Hello, 

 

I would like to know if there is a simple block diagram function that can detect if a signal is or was at 1? So a block diagram that has an output signal that is always at 1 from the moment where there is a rising edge on a signal. 

 

Thanks
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Altera_Forum
Honored Contributor II
‎08-14-2015 02:38 PM
691 Views

an or gate with the output connected to one of it's input is the simplest latch. Would require a power cycle to reset.

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Altera_Forum
Honored Contributor II
‎08-15-2015 06:25 AM
691 Views

You can also try the Dlatch primitive in the Quartus II.

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