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Valued Contributor III
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device size disproportional number of user IO pins

Hi, 

 

I have a question related to the number of user I/O for a the Cyclone IV E family for example, ....but I believe this issue may be common to other devices as well... 

 

Looking at the tables from the HandBook of Cyclone IV E I noticed a discrepancy between the device size and number of I/O which I cannot explain to myself: 

Following the increasing number of LE of a device size I noticed that the number of I/O does not depend on the number of LE.  

 

To be more precise with my question ¿shouldn't a larger device have a larger number of I/O? because in Altera it seems that the larger the device gets, the smaller the number of IO gets... why? (pag 1-5 table 1-3 from the Family Handbook) 

 

furthermore if you follow the prices of this particular family they grow linearly with the device size (which is perfectly normal, more logic = more $ in price), but the only thing that varies is the nr of I/O pins (when it should be more logic = more I/O = more $ <=> Altera has => more logic = less I/O = more $...why?) 

 

To give an example: see pag. 1-3 table 1-1 from Cyclone iv Handbook: 

Follow the Increasing number of LE and in parallel follow the MAX nr of I/O notice how strange it gets? 

The device EP4CE22 with 22 320 LE has the lowest number of IO =153 which is smaller than the number of IO of the smallest device EP4CE6 with 6,272 LE which has IO =179. 

 

The same thing can be noticed in: pag 1-5 table 1-3 from the Family Handbook following the packages in horizontal and the increasing device size in vertical. 

 

Can anyone explain this? Also I did't manage to find documentation related to this...  

¿Maybe you guys can help please? 

 

Cheers!
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Valued Contributor III
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Re: device size disproportional number of user IO pins

You mean within the same package? I believe in the smaller packages, there are probably more than enough I/O on the die, but only so many on the package. As the die gets larger, more VCC/GND connections are needed, which are added at the expense of user I/O. In the largest package(780) you see the I/O count get smaller and then larger again. I'm guessing this package isn't limited by the number of I/O on the package for the smaller devices but the number of I/O on the die, but that's just a guess.

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Valued Contributor III
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Re: device size disproportional number of user IO pins

Yes ...I mean within the same package but not only,... this phenomenon also happens for all device sizes including packages.... 

... in particular of interest to me (and I believe if I can explain this maybe I can find an explication for the rest of devices too) which also is the most peculiar case ...is why the device EP4CE22 (22,320 LE which is a "medium" size device) has a smaller number of I/O than the most smaller device EP4CE6 (6,272 LE) (pag. 1-3 table 1-1) ?... it makes no sense 😞 ... 

 

Furthermore ....I mean isn't this discordant with "Rent's rule" :confused: ? 

..the thing is that in Xilinx this is not happening....in Xilinx it is always the same no mater what device you choose: more logic = more I/O = more $...and it does agree with Rent's rule... more logic blocks => more IO 

 

... something is wrong...but I just can't figure out what....?.
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Valued Contributor III
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Re: device size disproportional number of user IO pins

Your post but would be better understandable, if you tell what you are exactly missing. 

 

To start with a trivial fact. While the number of LEs is a function of chip area, the maximum I/O pin count only grows according to it's edge length, because bond pads and I/O cells have to be placed at the chip border. 

 

Altera FPGAs are always designed to allow vertical migration within a particular package type. A larger chip with more IOs has also more ground pins. Apparently to provide maximum signal integrity, Altera decided to bondout all (or at least more) available ground pads. This results in less available IO's for the larger device in the same package.
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Valued Contributor III
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Re: device size disproportional number of user IO pins

...hmm...Yes that may be... 

 

Thank you guys for the quick replies!!!  

 

...I'm gathering some statistics to use with one of my own projects...and ...the purpose here would be to find out how exactly does Altera count the I/O pins in the documentation provided for the final users...  

 

I'am not contradicting what you guys said so far....but do you know if there is any documentation related to this on Alteras website....or..any other place? 

 

Cheers!
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Valued Contributor III
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Re: device size disproportional number of user IO pins

I doubt there's any documentation on it. I/O counts are obviously an important feature, and it's certainly annoying to see counts go down as you go to a larger device. (If you plan for possible migration using the migration devices option, then you're limited to the lower amount across all devices). That being said, it all seems pretty logical that all the necessary GND/PWR/Control/Dedicated signals are connected first, since they have to be, and the rest are used for I/O. As the die grows larger, more GND/PWR I/O are needed, and hence user I/O half to be sacrificed. 

As for comparing to Xilinx, who knows, but I'd be curious if you found out. Assuming the larger devices need more GND/PWR connections, yet the number are consistent throughout the family, then either the smaller devices are "over powered" (wasteful but not bad) or the larger devices are "under powered"(bad). Or maybe something else is at play. Either way, the numbers aren't going to change and you'll have to design within those constraints. Hope that helps.
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