Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18972 Discussions

digital simulation model for Altera SoC (Arria 10)

Altera_Forum
Honored Contributor II
1,136 Views

Hello, 

 

I am a functional verification engineer who is trying to verify as much as possible using Questa simulators prior going to the LAB. I am using UVM for custom logic verification. When integrated in the Altera SoC, the main verification will be done in the LAB. I am trying to shift some of my integration and bring up efforts to the simulation world rather than the LAB.  

Does Altera provide any digital simulation model for its SoC? I would like to simulate some code that I have written for ARM core in C, prior going to the lab. Is there a way to load the program into the memory and reset the ARM core to execute my code in simulation so I can clean up basic bugs prior to the lab?  

 

Any suggestion is highly appreciated.  

 

Regards, 

AA
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
323 Views

I don't think Altera provides a full SoC model. I would assume that it might be possible to gather some of the pieces like the core from ARM and the DesignWare components from Synopsys, but that would probably come with a hefty price-tag. Altera could provide their RTL in encrypted or compiled form somehow if they have a license to do so. 

 

I think your best bet will be to use AXI BFM's and/or UVM models and stimulate your FPGA fabric logic from there. 

 

Another option I've been thinking about is run an open source emulator like qemu under VPI/PLI. Then run the binary code under qemu and make some hooks to map to memory access to the FPGA fabric to AXI cycles. I've done this for a MIPS emulator in the past, but it's a considerable amount of work. Further, this will not get you models for the EMAC, SPI, and other specific hard functions found in the Arria 10 SoC. On the other hand qemu can run Yocto Linux today so it's quite capable.
bitstreamer
Novice
228 Views
Altera_Forum
Honored Contributor II
323 Views

Hi Petter, 

 

thx for your response, it makes sense. It does not seem very practical to get all these IP separately unless Altera gives all of them as one package.  

 

 

However, I came across below link in the Altera website and I am wondering whether this could be used for real software-driven simulation with custom RTL logic? Do we need to develop all the links between virtual platform and RTL? 

 

https://www.altera.com/products/soc/tools_and_software.tablet.html#virtual-platform 

 

Regards, 

AA
Reply