Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

dma transaction

Altera_Forum
Honored Contributor II
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when dma transfers data, will the data goes through avalon bus or just directly from memory to memory?? anyone can explain to me in detail how dma works? i want to check if my understanding on dma is correct or not. just to double check. thanks! besides, while dma is in progress, can cpu interrupt the transaction?

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Altera_Forum
Honored Contributor II
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DMA data goes from the master to the slave, through the Avalon fabric, which is a switched fabric, not really a bus. 

 

The CPU is not special, it's just another master. 

 

I'm not sure on what you mean by "interrupt". 

If by "interrupt" you mean "pause", depending on your SOPC is configured, one master accessing the fabric may cause another master to wait. 

 

If by interrupt, you mean "abort", then only if there a way for the CPU to talk to the master performing DMA telling it to abort.
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Altera_Forum
Honored Contributor II
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interrupt means like dma wants to transfer 1gb of data, then suddenly cpu needs to use the avalon... maybe saying like why dma transfer so long, then want to stop it...  

 

master to slave? what does it mean? sorry... i am a begineer.
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Altera_Forum
Honored Contributor II
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Avalon components can have "Master" ports and "Slave" ports. 

Master interfaces are the ones that take actions and they always talk to slave interfaces. 

 

The NIOS CPU, for example, only has a master interface. 

A memory component, for example, only has a slave interface. 

So, when the CPU reads/writes from/to memory, the CPU's master port talks to the memory's slave port. 

 

Back to your problem, there are two ways you can handle it, when you configure the Avalonm interface in the SOPC Builder. 

- You can have simultaneous multiple master/slave communications at the same time. 

- You can set different priorities to each master/slave pair, so the CPU has more priority than the DMA master.
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