does LVDS input clock have internal bias?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

does LVDS input clock have internal bias?

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I am AC coupling a clock into a S2GX device (but uses a regular CLK). Does this signal need to be rebiased to the appropriate common mode on the board, or can the FPGA bias it internally?

Thanks in advance!

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