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does LVDS input clock have internal bias?

Altera_Forum
Honored Contributor II
‎03-21-2007 09:52 PM
1,332 Views

I am AC coupling a clock into a S2GX device (but uses a regular CLK). Does this signal need to be rebiased to the appropriate common mode on the board, or can the FPGA bias it internally? 

 

Thanks in advance!
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