entity keyword

[Altera_Forum]

What is the difference between "entity" and "entity work" ? I am seeing these right before port map statements. I understand what an entity is but have never seen the word "work" follow it as a keyword. The book I have (1997 ish) does not describe this. 

 Thanks

[Altera_Forum]

what you are seeing is direct instantiation. 

 First of all, entity is used to declare an entity, probably what you've seen a million times in all the books:  entity my_ent is...  direct instantiation allows you to instantiate an entity without a component declaration via this method:  ent_inst : entity some_library.some_entity port map ( etc.  the local libary is work, so in your case you're seeing someone instantiate an entity from the same library this entity sits in.  The advantage of direct instantiation is that you dont need to maintain entity declarations and component declarations (basically the same thing) in two different places. Also, the code compiler will check the entity, rather than the component, so errors pop up immediatly rather than part way through synthesis.  This feature was brought into VHDL 1993, and as we all know there are many many many examples and VHDL engineers that even now refuse to acknowldge 20 years of VHDL advancement, and stick with legacy libraries and code ideas, mainly because its only in the last 10 years Vendors have pulled their finger out and started to embrace all the good ideas that came into the language. At least we're starting to see VHDL 2008 adoption now (over 2 years since the standard!)

[Altera_Forum]

direct instantiation is awesome 

 do note that you'll still need a component declaration for instantiating Verilog (or other sources)

[Altera_Forum]

--- Quote Start ---  direct instantiation is awesome   --- Quote End ---  Its good for quick-and-dirty checks of code, but it introduces a compilation-order dependence which can be annoying.  If the compiler sees  u1: entity work.mycomponent ...  before it has actually compiled mycomponent into work, then it will choke.  If however you have a component declaration either in the file where you use the component, or in a package that the code references, then the compiler will only look for mycomponent after it has processed all the VHDL files.  So, its 'awesome', but not perfect :)   Cheers, Dave

[Altera_Forum]

really? i can't believe i haven't run into that. i have been writing more Verilog lately 

 i can see the possibility for the interdependence problem