Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21585 Discussions

error when compiling

Altera_Forum
Honored Contributor II
1,371 Views

hi why is my altera coding is error when coding 

no waveform output.. 

is it something that i am missing from my project?? 

i only defined the VHD file 

 

Info: ******************************************************************* 

Info: Running Quartus II Analysis & Synthesis 

Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition 

Info: Processing started: Sun Aug 15 05:08:11 2010 

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off micop -c micop 

Info: Found 2 design units, including 1 entities, in source file seg7.vhd 

Info: Found design unit 1: SEG7-display 

Info: Found entity 1: seg7 

Error: Top-level design entity "micop" is undefined 

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings 

Error: Peak virtual memory: 212 megabytes 

Error: Processing ended: Sun Aug 15 05:08:15 2010 

Error: Elapsed time: 00:00:04 

Error: Total CPU time (on all processors): 00:00:01 

Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings 

 

any1 can help me??
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
640 Views

If your project is called micop, your toplevel need to have the same name.  

Whether it is HDL or schematic, make sure your toplevel also has the name micop. 

 

Success, Ton
0 Kudos
Altera_Forum
Honored Contributor II
640 Views

Dude, 

 

your toplevel name must be same name of your file, for example, if mine file name is micop.v the code have to be like: 

 

module micop (input x, output y); 

assign x = y; 

endmodule 

 

 

By  

Full Altera in Brazil
0 Kudos
Altera_Forum
Honored Contributor II
640 Views

If your project has many files it is good to right click on the top level file and execute the "set as top level" command. 

 

This eliminates problems if you changed the name of the file that contains the top level.
0 Kudos
Reply