Hi, all:
I wrote a verilog code to read the data from a external .txt file by using the read file function
readmemh. But there's some errors here. Hope someone can help me to finger out the problem.
Truly appreciate your kindly help.
Following is the code:
module readMemH_func (input clock, output wire [13:0] data_out);
parameter size = 1024; //data size
parameter fileName = "data.txt"; //target filename
reg [13:0] read_mem[1:size];
reg [13:0] temp;
integer addr_count = 1;
initial begin
$readmemh (fileName, read_mem, 1, size);
forever begin
always @(posedge clock) begin
temp <= read_mem[addr_count];
if(addr_count == size)
addr_count = 1;
else
addr_count = addr_count + 1;
end
end
end
endmodule
/*Error (10170): Verilog HDL syntax error at chirp.v(20) near text "always"; expecting "end", this is the error
message from my FPGA software. I tried to change the code several times, but nothing worked. I thinks there must
be a simple mistake here, but I cannot figure it out due to I'm a green hand on verilog. Thanks a lot for your
kindly help.*/
