functional simulation + STA = gate level simulation?

Altera_Forum · ‎02-15-2012

Hi:

Is "functional simulation" + "STA" = "gate level simulation"?

I designed a project,and run the functional simulation successfully,at the same time,the timequest timing analysis has no warning.So,need I run the gate level simulation? and why?

thank u!

Altera_Forum · ‎02-16-2012

No in general you don't need to run a gate level simulation, except if you have a bug on the running design that you think is linked to the compilation or a timing problem and want to track in down in the simulator.

If you are confident in your timing requirements specification, then the functional simulation and the Timequest report are enough.

Altera_Forum · ‎02-16-2012

Most people do not do timing/gate sims, just RTL + STA, as you describe. If you're doing funky circuits(non-synchronous and not recommended), timing sims may be helpful. They also might catch an incorrect timing constraint, such as a multicycle that really isn't. In general, STA is better thought since it covers a range of timing, i.e. all timing corners, while the timing simulations only do a specific one.

And in reality, the testing is RTL Sim + STA + Running in FPGA. That last one is key, and why ASIC designers might still do timing sims while FPGA designers usually do not.

Altera_Forum · ‎02-16-2012

thanks a lot！it helps me a lot!

Altera_Forum · ‎02-16-2012

ok.got it.Thanks a lot!

Altera_Forum · ‎02-17-2012

I usually also go directly from RTL to FPGA testing, when TimeQuest gives the green flag.

That said, there are a few caveats to keep in mind.

- You may have gotten your constraints wrong.

- There may be subtle inconsistenties between what you describe in HDL and what the synthesis tool produces.

Consider this trivial piece of VHDL when x is 'X'

y <= '1' when x = '1' else '0';

In RTL simulation, y will become '0'; post synthesis, y will become 'X'.

I don't recall ever coming across trouble with this when designing for FPGAs, only for ASICs. Best beware.

- There may be bugs/limitations in the synthesis tools and STA tools.

Ie, once upon a time in an old design, TimeQuest was missing a timing failure in totally normal register to register transfer in the same clock. But the bug showed up in gate level simulation (and in the FPGA).

PS: I have a very degree of confidence in TimeQuest. Don't want to start any flame war but I would not extend the same degree of confidence to lesser STA tools such as Altera's Classical Timing Analyzer or Xilinx's TRACE.

Altera_Forum · ‎02-19-2012

thank u for your advice,I'm confident with TQ ,too.