has anyone observed a programmer crash when S10 transceiver tile configured?

[Eugene_G_Intel]

has anyone observed any Stratix 10 issues during configuration when transceiver tiles are used? Our observation is If left unused, programming will be successful.

Only 1 of 4 transceiver tiles cause this problem. When one of 4 transceiver tiles are configured even with the simplest design, it will crash the programmer at 5% with an error log. Configuring other tiles and skipping the suspect one will make configuration pass as well.

This is from new board power up checking. Only 1 device is behaving this way but before we rule out the device, does anyone know if a signal (data or clock), or power level or connection problem can cause this behavior to the programmer?

[YuanLi_S_Intel]

Hi Eugene,

Can you check if your ref clock is supplied properly. There is a KDB for this.

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2019/why-does-the-configuration-fail-when-transceiver--pcie--hps-emif.html

Thank YOu.