help me to translate verilog to vhdl

[Altera_Forum]

hello, 

 is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl..  `timescale 1ns / 1ps  module mctrl(  input clk,  input rst,  output [31:0] wb_o_dat,  output wb_o_ack,  input [31:0] wb_i_adr,  input [3:0] wb_i_sel,  input wb_i_we,  input [31:0] wb_i_dat,  input wb_i_cyc,  input wb_i_stb,  output wb_o_err,  inout [31:0] GPIO,  input [31:0] GPIO_I );  wire sel_ram; wire sel_rom; wire sel_io; wire sel_ddr;  localparam RAM_BITS=11; localparam ROM_BITS=14; localparam IO_BITS=16;  wire [RAM_BITS-1:0] ram_addr; wire [ROM_BITS-1:0] rom_addr; wire [IO_BITS-1:0] io_addr;  wire [31:0] ramdata; wire [31:0] romdata; wire [31:0] iodata; wire ram_ack_o; wire rom_ack_o; wire io_ack_o;  wire rom_err; wire io_err;  wb_bram# ( .ASIZE(RAM_BITS) ) my_ram (  .clk ( clk ),  .rst ( rst ),  .ce ( sel_ram ),  .we ( wb_i_we ),  .addr( ram_addr ),  .dati( wb_i_dat ),  .dato( ramdata ),  .ack ( ram_ack_o ) );  wb_prom my_rom (  .clk ( clk ),  .rst ( rst ),  .we ( wb_i_we ),  .ce ( sel_rom ),  .addr( rom_addr ),  .dato( romdata ),  .dati ( wb_i_dat ),  .ack ( rom_ack_o ) );  wb_io my_io (  .clk ( clk ),  .rst ( rst ),  .ce ( sel_io ),  .we ( wb_i_we ),  .addr ( io_addr ),  .dato ( iodata ),  .dati ( wb_i_dat ),  .ack (io_ack_o),  .err ( io_err ),  .mask ( wb_i_sel ),  .GPIO ( GPIO ),  .GPIO_I ( GPIO_I ) );  reg ack_int;  assign ram_addr = wb_i_adr[RAM_BITS-1:0]; assign rom_addr = wb_i_adr[ROM_BITS-1:0]; assign io_addr = wb_i_adr[IO_BITS-1:0];  wire op;  assign op = wb_i_cyc && wb_i_stb;  assign sel_ram = op && (wb_i_adr[31:30] == 2'b11); assign sel_rom = op && (wb_i_adr[31:30] == 2'b00); assign sel_io = op && (wb_i_adr[31:30] == 2'b01);  assign wb_o_dat =  sel_ram ? ramdata :  sel_rom ? romdata :  iodata;  assign wb_o_ack = ram_ack_o | rom_ack_o | io_ack_o; assign wb_err_o = 0;  // synthesis translate_off  always @(posedge clk) begin  if (wb_i_we && sel_rom && wb_i_adr[31:5] != 0) begin  $display("%t: Invalid write to ROM: Address %h\n", $time, wb_i_adr[12:0]);  $stop;  end end // synthesis translate_on  endmodule

[Altera_Forum]

Why do you want to translate this code into VHDL? You may use it in Quartus II together with VHDL modules with no translation required. I have used mixed VHDL-Verilog implementation sometimes, and everything works well in Quartus.

[Altera_Forum]

because this code is written by other people and i do understand very little from verilog. thats why i want to convert it into vhdl because i can understand..

[Altera_Forum]

check this 

http://www.angelfire.com/in/rajesh52/verilogvhdl.html (http://www.angelfire.com/in/rajesh52/verilogvhdl.html)

[Altera_Forum]

--- Quote Start ---  because this code is written by other people and i do understand very little from verilog. thats why i want to convert it into vhdl because i can understand..  --- Quote End ---    Hi,  what is the description language of the instances wb_bram etc. Also verilog ? In this case a agree with OrchestraDirector not to convert the code, because it includes only a few instances and some logical gates.

[Altera_Forum]

yes...it's also verilog..did u mean that it can't be converted???

[Altera_Forum]

--- Quote Start ---  yes...it's also verilog..did u mean that it can't be converted???  --- Quote End ---    That's not the question. In case that the modules are tested ( should be used without modifications) I would not convert them to VHDL. You have to rerun all the testing again and compare it with the old results. That could be very time consuming, especially in case that the submodules are very complex.

[Altera_Forum]

Looking at that code, it doesn't seem too complicated and probably if you consult Wikipedia then you'll probably be able to bluff your way through it enough to produce a VHDL replica. Do consider how complicated the underlying blocks are though if you have to translate these as well. 

 All the advice against doing this is valid and pretty sensible but to add a few points the other way:  If you're relying on a free Modelsim licence then you won't be able to do mixed-language simulation. If you're including this block in a design then who is supporting it? Are you being expected to support a design in a language you don't understand? What are your timescales on the projects - if they're not tight then you may well find that re-writing this block in a supportable language and performing plenty of simulation to verify that you've done it right and can support the project long-term, might outweigh the risk of introducing a bug along the way.

[Altera_Forum]

--- Quote Start ---  Why do you want to translate this code into VHDL? You may use it in Quartus II together with VHDL modules with no translation required. I have used mixed VHDL-Verilog implementation sometimes, and everything works well in Quartus.  --- Quote End ---    How is it possible please ? I tried to do that, and when compiling, I have VHDL error syntax..  Ps: My file name is My_example_top.vhd should I change it to .v ?

[Altera_Forum]

What are you trying to achieve? VHDL code should be placed in *.vhd files, Verilog code in *.v. Both can be used together in a design.

[Altera_Forum]

but I have a syntax error when I'm compiling some verilog source (few lines) in a .vhd file ! 

The smart way, is to translate my few verilog lines to vhdl code..

[Altera_Forum]

--- Quote Start ---  but I have a syntax error when I'm compiling some verilog source (few lines) in a .vhd file ! The smart way, is to translate my few verilog lines to vhdl code..  --- Quote End ---    Hi,  you can't use verilog syntax in a VHDL-file. You need separate files for your VHDL and Verilog stuff.  Kin regards  GPK

[Altera_Forum]

--- Quote Start ---  The smart way, is to translate my few verilog lines to vhdl code..  --- Quote End ---   Yes, what's the problem for a few lines?