help on PLL input frequency

[Altera_Forum]

My source clock could range from 25MHz to 165MHz depending on the video format. Is there a way to ensure the PLL will lock onto it. I also need the output clock to be 90 degree shifted. 

 I don't think ATLPLL_RECONFIG will do what this. Any suggestion will be much appreciated.

[Altera_Forum]

BTW, I'm using Cyclone IV E.

[Altera_Forum]

I think, PLL reconfiguration would be the correct way to achieve the synchronisation to a wide input frequency range. Obviously you have to implement a rough frequency measurement to select the range. 

 Although the PLL MegaFunction setup is using an exact frequency specification, a PLL can basically lock over the 600-1300 MHz VCO frequency range for a fixed divider ratio, so 3 ranges would cover the said application. The loop filter settings are however representing a trade-off between different requirements and possibly not optimized for a wide lock range. You'll find some articles in the Altera knowledgebase discussing lock range optimization: http://www.altera.com/support/kdb/solutions/rd01152007_962.html  The actual lock range for a particular PLL setup is shown in the fitter report. I ususally see a 1:2 lock range with Cyclone III projects, I guess it's similar with Cyclone IV.

[Altera_Forum]

I have looked at the PLL lock range in the Fitter report and you're right, I see almost 1:2 lock range. Because in my design, the input ranges from 25MHz to 165MHz, that's why I need some help from your guys. 

 I will check the link you provided, and thank you for your comment/suggestion.

[Altera_Forum]

I read that solution yesterday. What that method do is it helps you extract valid parameter values for the PLL. You can put in Fmin for clko and Fmax for clk1, it tells you if your input goes beyond the lock range that the PLL is capable of, so it is not what I'm looking for.

[Altera_Forum]

--- Quote Start ---  so it is not what I'm looking for  --- Quote End ---  Seems like you are looking out for a too convenient way. I provided the link just to show, that a 1:2 lock range can be achieved for a fixed PLL setting. The other point I told is, that frequency measurement and range switching by PLL reconfiguration is required for a wider range than 1:2. I'm not aware of ready-to-use design examples for DVI or whatever your application is. But I'm sure it can be done, you just have to figure it out.  Perhaps a forum member has already designed a similar solution and is willing to share it. Unfortunately I don't have it.

[Altera_Forum]

I know and I guess I will have to come up with something to work around this. Thanks for your comment.