- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
What is "zero" doing in this program.
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit IS
port(a, b : in std_logic_vector(7 downto 0); -- a and b are busses
op : in std_logic_vector(2 downto 0);
zero : out std_logic;
f : out std_logic_vector(7 downto 0));
END alu8bit;
architecture behavioral of alu8bit is
begin
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" =>
temp := a and b;
when "100" =>
temp := a and b;
when "001" =>
temp := a or b;
when "101" =>
temp := a or b;
when "010" =>
temp := a + b;
when "110" =>
temp := a - b;
when "111" =>
if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others =>
temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
f <= temp;
end process;
end behavioral;
Also see the fist case "000" what does it mean by a and b. When I test this condition I always get the result of b?
Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
It looks like a simple ALU.
op is the opcode. SO when op is 000 the ALU performs a logical AND of a and b, When Op is 001 it performs a logical OR etc The result of the operation is stored in the variable temp. The signal zero is one when the result in temp is 0. i.e. it indicates that the result of the requested operation (AND, OR, +, -) etc is zero. When you say you always get the result of b, what value is a?
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page