help with clock

[Altera_Forum]

I need to run a clock signal through a regular IO and then lock on to it using a PLL. Quartus doesn''t seem to like me doing this. Has anyone done this before and if so, how did you get it to work? Thanks. 

 I'm using a stratix II

[Altera_Forum]

Apparently you are running into this restriction in the footnotes for figures 1-3 and 1-7 in the Stratix II handbook Volume 2: "An internally generated global signal cannot drive the PLL." 

 Given what the device does support, I expect that what you want to do is possible in hardware. You might be able to get a Quartus INI variable to allow it (with no guarantees about jitter or whether the PLL will lock). You need to file an SR through MySupport to request that.

[Altera_Forum]

Only dedicated clk pin and another PLLOUT could feed