how can i connect the VREFB pins of EP3C40F324

[Altera_Forum]

I want to connect a DDR SDRAM to bank3 and bank4 of EP3C40F324, the interface is SSTL_2, except data,address,command signals, and i need a 1.25V reference, but there is four VREFB pins in one bank of EP3C40F324, should i connect all four VREFB pins to VCC125, or just VREFB pins in group that DQ belongs to? 

 please help me, thanks a lot!

[Altera_Forum]

From the Cycclone III handbook: 

  --- Quote Start ---  If you do not use all of the VREF groups in the I/O bank for voltage referenced I/O standards, the VREF pin in the unused voltage referenced groups can be used as regular I/O pins.  --- Quote End ---      --- Quote Start ---  When VREF pins are used as regular I/Os, they have higher pin capacitance than regular user I/O pins. This will have an impact on the timing if the pins are used as inputs and outputs.  --- Quote End ---    Additionally, you have to keep the placement rules for voltage referenced I/O standards. B.T.W., address and command lines are also using a voltage reference SSTL-2 Class I standard with DDR RAM. I didn't see an explicitely statement in the handbook, if VREF is also needed for SSTL output only pins, I would follow the Quartus Pin Planner in this regard.

[Altera_Forum]

--- Quote Start ---  From the Cycclone III handbook:         Additionally, you have to keep the placement rules for voltage referenced I/O standards. B.T.W., address and command lines are also using a voltage reference SSTL-2 Class I standard with DDR RAM. I didn't see an explicitely statement in the handbook, if VREF is also needed for SSTL output only pins, I would follow the Quartus Pin Planner in this regard.  --- Quote End ---     I'm very appreciated to your reply! 'address and command lines are also using a voltage reference SSTL-2 Class I standard with DDR RAM' , that is to say all four VREFB pins in one bank should connect to the VCC125? in this case,another question occurs, all pins in bank3 and bank4 is not enough for DDR sdram, that means I should use another banks for connection of the DDR, is that right?  another question,what is B.T.W.?   I'm really a beginner,give me some suggestion. thank you for your help!

[Altera_Forum]

As I said, I'm not sure if address and command output pins need VREF, but they obviously should use SSTL-2 Class I. I have a SODIMM DDR2 design, but DQ pins are spread over all VREF groups of the two involved banks, so I didn't have to think about using all VREF pins or not. B.T.W. (by the way) is just a typical U.S. english 3 letter short cut.

[Altera_Forum]

I have known what's your meaning, and I have to make a decision. 

thank you!

[Altera_Forum]

From CycloneIII Device Family Pin Connection Guidelines, we can see that: All of the VREF pins within a bank are shorted togetherl. 

 but from CycloneIII EP3C40 Device Pin-out,we can't see the similar description. just a littile unreasonable.

[Altera_Forum]

If they would be shorted together, they couldn't be used as individual I/Os, but they can. Thus this description is generally incorrect. However, as I said, I'm not sure what is required with voltage referenced I/O standards, that have only outputs in a VREF group. I would simply follow the Quartus pinout file in this point.

[Altera_Forum]

Thanks for your reply. 

I have just finished the schematic diagram of DDR recently. But now, I'm confused. Thanks for your remind, And I don't understand 'I would simply follow the Quartus pinout file in this point.' clearly. you mean I should run the command that Start I/O Assignment Analysis? Can you give me a more detailed description?  Thank you!