how do I generate 32k clock from cyclone V pll

[Altera_Forum]

Hi, 

  How do I use altera pll to generate 32k frequency in cyclone V? I need help for this one.  Thanks

[Altera_Forum]

Have you read this? www.altera.com/literature/ug/altera_pll.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=altera_pll (http://www.altera.com/literature/ug/altera_pll.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=altera_pll) 

 From the Cyclone V handbook:  Each Cyclone V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match fin × (M/N).  For Cyclone V, each of M,N,C can be 1..512.  So if your input clock is 50MHz (as an example), then with M=2, N=125, C=25 will give an Fout of 32KHz (ie, 50e6*2/(125*25)).

[Altera_Forum]

--- Quote Start ---  Have you read this? www.altera.com/literature/ug/altera_pll.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=altera_pll (http://www.altera.com/literature/ug/altera_pll.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=altera_pll)  From the Cyclone V handbook:  Each Cyclone V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match fin × (M/N).  For Cyclone V, each of M,N,C can be 1..512.  So if your input clock is 50MHz (as an example), then with M=2, N=125, C=25 will give an Fout of 32KHz (ie, 50e6*2/(125*25)).  --- Quote End ---     Hi,   The PLL output frequency only gives me lowest value to 1.1718Mhz, and can't go lower than that. Is there any other way to let me generate 32k from altera PLL?  Thanks, Jeff

[Altera_Forum]

The IP catalog has a module for a PLL generated clock. It will calculate the parameters needed to get your desired frequency or the closest available.

[Altera_Forum]

--- Quote Start ---  The IP catalog has a module for a PLL generated clock. It will calculate the parameters needed to get your desired frequency or the closest available.  --- Quote End ---    Hi,   Thanks, but it seems to me that it is impossible to get 32K from altera PLL directly.  -Jeff

[Altera_Forum]

Use the 'counter out to out cascade mode' of the Cyclone V PLL. 

 For a 50MHz ref clock input (for example), use a multiply by 4 and divide by 25 to generate an 8.0MHz clock on pll_output_0.  Then use pll_output_0 to pll_output_1 cascade mode with a division factor of 250 to generate 32.0KHz ( = 8.0MHz / 250 ) on pll_output_1.

[Altera_Forum]

--- Quote Start ---  Use the 'counter out to out cascade mode' of the Cyclone V PLL.  For a 50MHz ref clock input (for example), use a multiply by 4 and divide by 25 to generate an 8.0MHz clock on pll_output_0.  Then use pll_output_0 to pll_output_1 cascade mode with a division factor of 250 to generate 32.0KHz ( = 8.0MHz / 250 ) on pll_output_1.  --- Quote End ---    Hi,   If I did this way, I got some error message like  "the specified configuration causes VCO to go beyond the limit", and don't allow me to click finish button. what happen?  Thanks, Jeff

[Altera_Forum]

The device handbook describes the limits for the PLL constants. You must stay within those limits. I suspect 250 is too large a divisor.

[Altera_Forum]

Minimum VCO frequency is 600MHz, so multiply by 4 is too little.

[Altera_Forum]

For low frequencies, you would typically make a clock that is a power of two multiple of the clock frequency you want, and then use clock divider logic (which is simplified by having power of two) to generate either a clock enable signal (if you don't need a 50% duty clock), or a clock signal itself (if jitter and phase relationship is not of concern).

[Altera_Forum]

--- Quote Start ---  Minimum VCO frequency is 600MHz, so multiply by 4 is too little.  --- Quote End ---    Ok, so then multiply by 16 (=4*4) to get 800MHz and then divide by 100 (=4*25) to get 8MHz clock, which can then be divided by 250 to get 32KHz.  All the multiply / divide counters are 9 bit (range 1..512) on the Cyclone V PLLs per the handbook, so 250 should work just fine.

[Altera_Forum]

@ak6dn Doesn't work like that... The first multiply/divide counter (M/N) sets the VCO frequency. The VCO frequency must be at least 600MHz. 

 The lowest frequency the PLL output will do is around 1.6MHz. For lower clock frequencies, this should be done in logic, either to make a clock enable, or a low frequency clock as I said in my earlier post.

[Altera_Forum]

--- Quote Start ---  @ak6dn Doesn't work like that... The first multiply/divide counter (M/N) sets the VCO frequency. The VCO frequency must be at least 600MHz.  The lowest frequency the PLL output will do is around 1.6MHz. For lower clock frequencies, this should be done in logic, either to make a clock enable, or a low frequency clock as I said in my earlier post.  --- Quote End ---    That is true for a single, direct PLL output clock. However, for Cyclone V you can use 'cascade counter mode' where you take pll_output_0 at 8.0MHz, for example, and use that as the source clock to pll_output_1 in cascade mode, and then set the divisor to (in this case 250) to generate 8MHz/250 = 32KHz on pll_output_1. It takes two PLL outputs to do this, but it allows for much higher clock division ratios (ie, up to 512*512).  Reference, ALTPLL IP User Guide, version 2014-08-18, page 28:    --- Quote Start ---  pll output counter cascading  In 28 nm devices, a C-counter input can be either a VCO output or the cascaded output of a neighboring C-counter. Cascading C-counters increase the possible division factor, enabling very low frequency PLL output clocks.  --- Quote End ---    In the QSYS IP wizard, select two PLL clock outputs, and tick the 'cascade mode' box on output 0 to feed it into output 1 source.  Ok, here it is in Quartus 16.0:  http://www.alteraforum.com/forum/attachment.php?attachmentid=12556&stc=1

[Altera_Forum]

--- Quote Start ---  The device handbook describes the limits for the PLL constants. You must stay within those limits. I suspect 250 is too large a divisor.  --- Quote End ---    Hi,   Thanks for the replying. every one here is correct but I find when I choose "Enable physical output clock parameters" which can show M,N.C values, it doesn't allow me to "finish". Does any one know why?  Thanks, Jeff

[Altera_Forum]

It should be generating an error message in the 'message' window if it does not like some parameter value or values. 

 You might have to take a screen shot of the problematic window and post it.  What version of Quartus are you using?

[Altera_Forum]

--- Quote Start ---  That is true for a single, direct PLL output clock. However, for Cyclone V you can use 'cascade counter mode' where you take pll_output_0 at 8.0MHz, for example, and use that as the source clock to pll_output_1 in cascade mode, and then set the divisor to (in this case 250) to generate 8MHz/250 = 32KHz on pll_output_1. It takes two PLL outputs to do this, but it allows for much higher clock division ratios (ie, up to 512*512).  Reference, ALTPLL IP User Guide, version 2014-08-18, page 28:    In the QSYS IP wizard, select two PLL clock outputs, and tick the 'cascade mode' box on output 0 to feed it into output 1 source.  Ok, here it is in Quartus 16.0:  http://www.alteraforum.com/forum/attachment.php?attachmentid=12556&stc=1   --- Quote End ---   Hi,   I got it. Thanks a lot.  -Jeff

[Altera_Forum]

Hi, 

  I got 32k finally. Thanks everyone.  -Jeff

[Altera_Forum]

@ak6dn. Did not know that. Thanks, very informative! :)

[Altera_Forum]

--- Quote Start ---  @ak6dn. Did not know that. Thanks, very informative! :)  --- Quote End ---    Altera does not always make it easy to find new and useful features :(