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http://www.alteraforum.com/forum/attachment.php?attachmentid=12552&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12553&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12554&stc=1 I hope to probe the lvds input signal 'ad_data[13:0]' in the .stp file,but the compile will fail when the ad_data[13:0] are added in the stp.
How can I solve it?
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I'm actually not surprised by this as those signals have no clock and exist ONLY in the I/O buffer as the alt_lvds block is instantiating components in the IOB, not the true FPGA fabric. Monitoring signals before the LVDS block if using the alt_lvds is not really very useful, particularly depending on the speed of the signals.
In addition, be careful of bitslip concern with the LVDS data.
Happy to help if you have any issues with the LVDS inputs.
