how many ALTCLKCTRL can be used in Stratix IV decice

[Altera_Forum]

I find the there is about 16 PLL in Stratix IV, but how many ALTCLKCTRL can be used in Stratix I? It's no limitation?

[Altera_Forum]

I think, ALTCLKCTRL can be used in all places, where dynamic clock switching is supported by the respective FPGA. It represents the clock multiplexers, that are provided by the hardware. The Stratix IV manual should tell precisely.

[Altera_Forum]

Thanks. i go through in handbook, This cell should not be limited

[Altera_Forum]

there is a limit: 

   --- Quote Start ---  Every GCLK and RCLK network has its own clock control block.  --- Quote End ---