how to clear the ram content in one clock?

Altera_Forum · ‎08-06-2008

hi all,

I used RAM ip core or the RAM verilog code I written, and want to reset all the content of the memory to 0. I only find the way to write one zero at corresponding address of the RAM in one clock. So to clear a RAM with 1024 depth needs 1024 clocks, it cost too much time. Anybody has good method to clear it in one clock?

I even rewrote the ram using verilog code, if adding the clear function, it can't be synthesize to block RAM of the altera FPGA. What's the matter here?

this is the code:

////////////////////////////////////

module dpram (

clk_i,

clear_i,

wen_i,

addrin_i,

d_i,

clkout_i,

addrout_i,

d_o

);

parameter DWIDTH = 16;

parameter AWIDTH = 16;

parameter DEPTH = 64;

input clk_i;

input clear_i;

input wen_i;

input[AWIDTH-1:0] addrin_i;

input[DWIDTH-1:0] d_i;

input clkout_i;

input[AWIDTH-1:0] addrout_i;

output[DWIDTH-1:0] d_o;

reg[DWIDTH-1:0] mem[DEPTH-1:0];

reg[AWIDTH-1:0] addrb_reg;

integer i;

//if remove clear function, the dpram can be synthesized to ram block

always @(posedge clk_i ) begin:clear

if (clear_i) begin

for(i=0; i<DEPTH; i = i+1)

mem[i] <= 0;

end

always @(posedge clk_i )

begin:wr

if (wen_i) mem[addrin_i] <= d_i;

end

always @(posedge clkout_i)

begin:rd

addrb_reg <= addrout_i;

end

assign d_o = mem[addrb_reg];

endmodule

///////////////////////////////////////////

Altera_Forum · ‎08-06-2008

There is no way to clear all the contents of a RAM. I don't think any FPGA can do that, and it's probably just too expensive silicon-wise. If you really need it, you'll have to do something in logic. Some thoughts:

- Clear every location as you suggested.

- Duplicate the RAM. When you issue an aclr, you really just switch to the other RAM who had it's contents cleared, and your logic then begins clearing the old RAM. As long as you don't issue an aclr less than 1024 clocks apart, that should work.

- Make the RAM one bit wider. Have a toggle register that powers up to 0 and writes to that extra bit. When ever you read from a location, compare the extra bit of the word to the toggle register. If they're equal, use the word, and if they're not make the word all 0s(because it hasn't been written to since the last clear). Whenever you issue a new clear, just toggle the register. (Thinking about it some more, this would only work if you know you're going to write to every location between clears. If not, then a word that hadn't been written to in two clears would now look like it had been written to since the last clear, even though it hadn't.)

Anyway, just some ideas. I'm sure there are more...

Altera_Forum · ‎08-06-2008

One method, although expensive is to have a register bit for every ram location. When you write to the register, you write the register bit to '1', at aclr, you clear the entire register. Any reads with the control register bit =0, would read zero, otherwise they read their value.