how to config fpga with flash?

[Altera_Forum]

hi , i am Tig , a starter . 

 and my board is Nios II Embedded Evaluation Kit, Cyclone III Edition.  the flash device is cfi_16M.  i want to know how to use flash config the fpga  i have read the document "using Parallel Flash Loader "  but i am confused by the relationship between the fpga & cpld  actually , i don't know how to assign the pins  i tried to convert .sof to .jic , however , the board doesn't support EPCS  so ,   thanks all

[Altera_Forum]

Hi, 

 There are two types of Parallel Flash Loader(PFL). One is implemented to MAX II or other CPLD. It writes data from JTAG to Flash and loads data from Flash to any FPGA device. A function writing data from JTAG is called programmer, and one loading to FPGA is called loader. Another is implemented to FPGA. It writes data from JTAG to Flash and is programmer only. Loader? Only the Cyclone III FPGA has dedicated loader circuit to load from Flash, and this must be the way to configure FPGA in your board. It is described in AN-478. Probably you can use the "Factory Default PFL", so you just convert sof to pof instead of jic. All the pins for PFL are dedicated in the Cyclone III, so you don't need to assign them.  Thanks,

[Altera_Forum]

You have to convert the programming file in active parallel setting to file type *.pof.

[Altera_Forum]

thank u a lot. 

 can i use the Signaltap II to detect the signals  after programming the *.pof into flash device?  :)

[Altera_Forum]

Not for debugging the configuration process.

[Altera_Forum]

so , that means the Singnaltap is disabled ? 

 thanks

[Altera_Forum]

SignalTap can start operation at the earliest with start of user mode (with Power-Up Trigger), cause it's part of the design. But you didn't exactly tell, what you are trying to achieve with SignalTap.

[Altera_Forum]

i want to get the timing of the DDR on the board .

[Altera_Forum]

OK, that isn't conflicting with flash configuration anyhow. But you have the restriction that you can't capture signals directly at double data rate pins (DDIO registers) respectively with double data rate general. So you can't see the particular DDR timing, but you can see of course the sequences of control signals and addresses, and indirectly the RAM read and write data at the demultiplexed "slow" side of DDIO.

[Altera_Forum]

yes ,  

 i just want to see the control singals , addresses & data.  they can let me know if the design is right .  thanks a lot   :)