how to configure & initiate one FPGA by using another FPGA?

[Altera_Forum]

through a JTAG... 

Is there any detailed timing diagrams ? Thanks in advance!

[Altera_Forum]

Basic JTAG timing informations can be found in the boundary scan chapter of Altera device handbooks. For the generation of Altera private configuration JTAG commands, you can e.g. refer to the JRunner project, see AN414 and respective code examples.

[Altera_Forum]

Are You sure You need to do it using JTAG? I'd offer to use Passive Serial mode.

[Altera_Forum]

okay, passive serial mode is okay, could you please tell me the detailed timing diagrams for the passive serial mode? thanks a lot!

[Altera_Forum]

This should be documented on altera.com, but I've heard that people using this mode up to relatively high speeds (10Mbps?)... So I doubt timing will be issue here :)

[Altera_Forum]

thanks for your quick reply, I will try to find if there are enough documents....

[Altera_Forum]

SRunner project, see AN418.

[Altera_Forum]

okay, I will read it soon, thank you very much !

[Altera_Forum]

--- Quote Start ---  SRunner project, see AN418.  --- Quote End ---    I read the AN418, it seems that the file format there is .rpd, however, my source file is in the format of .hexout..... and the configuration handbook only mentions .rbf .sof .pof .hexout .jam.... what is .rpd ?

[Altera_Forum]

I don't see such file type output like .rpd in available options. Are You sure it's FPGA bitstream image? I've tested using .ttf and bitbanging it from microcontroller - works fine.

[Altera_Forum]

I reviewed AN418 and found, that it actually describes EPCS chip programming rather than FPGA passive serial configuration. I apalogize for the confusion. Most people use binary *.rbf files or e.g. *.ttf for passive serial.

[Altera_Forum]

--- Quote Start ---  I don't see such file type output like .rpd in available options. Are You sure it's FPGA bitstream image? I've tested using .ttf and bitbanging it from microcontroller - works fine.  --- Quote End ---    Thanks. Did you ever try the .hex file to configure and initiate ?

[Altera_Forum]

--- Quote Start ---  I reviewed AN418 and found, that it actually describes EPCS chip programming rather than FPGA passive serial configuration. I apalogize for the confusion. Most people use binary *.rbf files or e.g. *.ttf for passive serial.  --- Quote End ---    Thanks for your kindness and no need to apologize at all !!!

[Altera_Forum]

Yes, and I do this all the time. If FPGA# 1 is configuring FPGA# 2, use four I/O pins from# 1 and connect them to dedicated JTAG pins of# 2. Then to program the FPGA# 2 directly, you can use the industry standard SVF file and Altera's Jrunner software to bit bang the I/O pins. In addition, if you want FPGA# 1 to program an EPCS flash, connect I/O pins from# 1 to Active Serial port of EPCS flash, and then you can use the RPD file and again Altera's Jrunner software to bit bang the active serial pins in FPGA# 1. Both the SVF and RPD file can be converted from SOF and POF using the Altera's conversion tool in Quartus II. 

       --- Quote Start ---  through a JTAG... Is there any detailed timing diagrams ? Thanks in advance!  --- Quote End ---