how to connect fpll output to transceiver transmit clock

[Altera_Forum]

My design is such that I will require all transceiver channels to be full duplex(both transmit and receive). I have instantiated a PCIexpress module with uses one of the channels as a global PLL for the bonded x4 pciexpress transmitter PLL. I however do not want to use this channel as transmitter PLL(it will be used for another high speed link later) I have read in a lot of Altera literature that it is possible to use the normal fpll for clocking the transmitter up to a speed of about 3Ghz). This will meet my requirement but the big question is how do I connect the fpll output to the transceiver? 

Using Arria V SoC

[Altera_Forum]

Hi, just wonder which IP core that you are using to instantiate the PCIe module? My understanding with PCIe IP core is generally limited by the option provided by the IP ie which TX PLL to use. You might need to explore using Native PHY if you want to use fPLL as TX PLL. However, you might need to build all the other required PCIe logics if you are using Native PHY.