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I use FPGA to connect a ASIC,to receive bus data(video raw data).The Receive clock is from External ASIC.
For the external video is unknown so that the sync clock frequency is unknown.
And,How to constrain this unknow clock?
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How on earth can anybody constrain unknown clock? you need to know the clock frequency as well as input data offset from clock edge at fpga pins otherwise you are asking the impossible.
