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Altera_Forum
Honored Contributor I
760 Views

how to declare 2D array in package and the same i want to use

HOW TO DECLARE 2-D ARRAY FOR MEMORY IN PACKAGE. 

THE SAME VARIABLE I WANT TO USE IN OTHER PLACE WHERE I AM CALLING THAT PACKAGE. 

 

 

library ieee; 

use ieee.std_logic_1164.all; 

 

 

package constant_package is 

constant DATA_WIDTH : integer; 

constant ADDR_WIDTH : integer; 

subtype word_t is std_logic_vector ((DATA_WIDTH-1) downto 0); 

type memory_t is array (2**ADDR_WIDTH-1 downto 0) of word_t; 

end constant_package; 

 

 

package body constant_package is 

constant DATA_WIDTH : integer := 8; 

constant ADDR_WIDTH : integer:=8; 

end constant_package; 

 

 

THIS IS WHAT MY CODE IS IT OKK???
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Altera_Forum
Honored Contributor I
28 Views

It is ok. You can declare your type as follows for more simplicity. 

type memory_t is array (2**ADDR_WIDTH-1 downto 0) of td_logic_vector ((DATA_WIDTH-1) downto 0); 

 

use your package in other files. You can even define port types as memory_t (Beauty of VHDL)!
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