how to map transceivers with PCIe Hard IP

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

how to map transceivers with PCIe Hard IP

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I have 2 doubts:

1.Stratix 4 GX contains 4 hard IP PCIE blocks. I want to know , among the 48 transceivers which 4 transceivers is allocated to the 4 Hard ips . is there a way to find this in quarus tool.

2. what is the Difference between Avalon ST and Memory interface. and when wh it is used?.

Regards

vengadesh

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