how to set timing constraint for clock

[mappy5]

In the case of the circuit shown in the figure, how should the timing constraint be set?

Do CLK_1 and CLK_2 need timing constraints?

create_clock -name {in_CLK} -period 20.0 [get_ports {in_CLK}]

create_generated_clock -name {CLK_half} -source [get_ports {in_CLK}] -divide_by 2 -master_clock {in_CLK} [get_nets{CLK_half}]

[mappy5]

[sstrell]

Yes, all clock domains need constraints.  

If you are using a PLL to create these clocks, you can simply use derive_pll_clocks.  If you are not using a PLL, you will need additional generated clock constraints for clk_1 and clk_2 (and possibly that other clock that generates clk_1 and clk_2).

See the unconstrained paths report in the timing analyzer to see which clocks are considered unconstrained, if any.

[mappy5]

hi, Thank you for answering.

PLL is not use.

Generate the clock with the logic I created.

clk_1 is 132Hz

clk_2 is 339Hz

Clk_1 and clk_2 were not pointed to unconstrained paths in the timing analyzer.

Is there no timing constraints for such a low speed clock?

[sstrell]

Unconstrained clocks are reported based on them driving the clock inputs of registers or other clocked logic.  Even super slow clocks should have timing constraints for completeness.  

[mappy5]

Is this the right way to set timing constraints on CLK_1?

create_generated_clock -name CLK_1 -source [get_registers {yyy:xxx|half_1}] -divide by 245760 [get_registers {yyy:xxx|CLK_1}]

 

[sstrell]

Yes, that's the idea, though like I said, you probably have to create a clock for half_1 as well.