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How to show " A to F " ???
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mini is port ( en, m_reset, UP_DW, clk : in std_logic; q : out std_logic_vector (3 downto 0)); end mini; architecture flow of mini is signal count_sig :unsigned (3 downto 0); begin process ( en, m_reset, UP_DW, clk ) begin if (en = '1' and m_reset = '1') then count_sig <= "0000"; elsif(en = '0' and m_reset = '1') then count_sig <="0000"; elsif falling_edge (clk) and UP_DW = '0' then count_sig <= count_sig +1; elsif falling_edge (clk) and UP_DW = '1' then count_sig <= count_sig -1; end if; end process; q <= std_logic_vector (count_sig); end flow;Link Copied
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You need HEX-to-7-segment decoder.
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so i need to write this ?
with up_dw select output <= "00000001" when "0000" "10011111" when "0001" and so on ?? do i need to write this ? singal output : std_logic_vector (6 downto 0) ??- Mark as New
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Yes. By convention, segments are a to g.

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