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Hi,
My problem is : I have a custom board, FPGA cyclone III and Flash connect with AP scheme idea, but MSELs were set wrong (all GND) I have to use Jtag to config FPGA each time turn on the board (it worked). I need to test or to talk with the Flash (P33) as a normal memory for FPGA to launch a signal processing application and get data from this board. Please tell me how should I do? as I understand with little change of some pins to be high or low such as nconfig data0 and DCLK I dont have to do any thing with hardware stuff. What I have to care is set up with Nios and Quartus? thanksLink Copied
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