I used to programe like this : use rising edge of clk to output one data,and then use falling edge to capture data at next step,because I think if the data is align at the rising edge of clk,i can capture them safely,but now I found I was wrong,the programe rule is use one edge all then time. then something not clear happens to me,this is : when I use dsp core in fpga,it requre the input clk align to the center of data at rising edge,but the data is output at rising edge .how can I do . And something I thought is : there is no need of the hold time when i capture data.
