how to write code to realize n times frequency?

[Altera_Forum]

Hi,all! 

I want to know how to write code to realize n times frequency? There is no PLL/DLL in some CPLDs, So in this sitution I need to write a short hdl code by myself to realize the same function about PLL/DLL.  I have no idea, maybe you can give me some! Thanks!

[Altera_Forum]

In order to multiply the frequency you need a fast oscillator (this can be done) a phase detector (this also can be done, perhaps) 

and a method to modify the oscillator frequency (very difficult in FPGA).  Even if it works the performance should be very poor.  What about using an external PLL/DLL component?

[Altera_Forum]

--- Quote Start ---  In order to multiply the frequency you need a fast oscillator (this can be done) a phase detector (this also can be done, perhaps) and a method to modify the oscillator frequency (very difficult in FPGA).  Even if it works the performance should be very poor.  What about using an external PLL/DLL component?  --- Quote End ---   Thanks for your reply! Yes，you're right. It's OK to use an external PLL/DLL, but It maybe a little complex if we don't have an external PLL/DLL and can't use the CPLD/FPGA's existing resources.  Now I only want to know how to use code to realize it. and I believe It's workable.

[Altera_Forum]

A PLL has analog components, that can't be represented by "code", the VCO (physically a differential ring oscilator with variable supply voltage), phase detector and loop filter. In some cases, it can be solution to generate a double frequency clock by processing both edges of the input clock with logic gate delay chains or external delay circuits. 

 The feasibility depends of course on the clock signal specification and available resources.

[Altera_Forum]

Okay! I see 

you said, "In some cases, it can be solution to generate a double frequency clock by processing both edges of the input clock with logic gate delay chains or external delay circuits." I heard before from a book, but not in detail . Do you have a document or something else about how to realize it? many thanks!

[Altera_Forum]

Simply think about CLK2 = CLK1 XOR delayed(CLK1)

[Altera_Forum]

--- Quote Start ---  Simply think about CLK2 = CLK1 XOR delayed(CLK1)  --- Quote End ---   Wow! I got it. thanks!